;*************************************************************************** ;* ;* Title: SO2R Antenna controller boot table/code loader ;* Version: 1.0 ;* Last updated: 13 April 2010 ;* Target: ATMega328P ;* ;* DESCRIPTION ;* ;* This implements the bootloader for the YCCC Antenna Switch Box ;* ;* ;************************************************************************** ; ; Commands ; ; '$' Status query ; Returns version number (1 byte) ; ; 'W' Write a page of flash ROM ; Receives 2 byte of address (low first) ; Receives 64 bytes of data ; Receives 1 checksum byte (sum of previous 66 bytes) ; Returns status ; ; 'R' Read a page of flash ROM ; Receives 2 bytes of address (low first) ; Returns status ; Returns 64 bytes of data ; Returns a checksum byte (sum of previous 64 bytes) ; ; '0' Boot ; Start the program at address 0. ; ; Return Status ; ; 'B' Bad page write ; 'C' Page write data checksum ; 'X' Communications error ; 'Y' Successful ; '?' Unknown command .INCLUDE "m328Pdef.inc" ; Include Register/Bit Definitions for the mega328P ;***** Register definitions .def ML = r0 ; Low order multiplier result .def MH = r1 ; High order multiplier result .def C = r16 .def T1 = r17 ; High register temporaries .def T2 = r18 .def COUNT = r19 .def ERR = r20 .def ACTIVITY = r21 .equ RSTR = PORTB0 ; Relay strobe .equ ISTR = PORTB1 ; Inhibit strobe .equ RSER = PORTB3 ; Relay data .equ RCLK = PORTB5 ; Relay clock .equ RS232RX = PORTD0 ; RS-232 Receive .equ RS232TX = PORTD1 ; RS-232 Transmit .equ ICLK = PORTD4 ; Inhibit clock .equ ISER = PORTD5 ; Inhibit data .equ BOOTB = PORTD6 ; Bootloader button .equ UBR = 12 ; Baud rate = 76.8 kbps with fCK = 16 MHz .equ RAMPAGE = 0x100 ; Start of page of RAM used as a buffer .equ PAGESIZEB = PAGESIZE*2 ; PAGESIZEB is page size in BYTES, not words .equ MY_BOOTSTART = FIRSTBOOTSTART ; 512 bytes of boot loader ;***** Boot loader .org MY_BOOTSTART ; bootstart address according to .equ above ; Set the stack to the end of RAM ldi T1, high(RAMEND) out SPH, T1 ldi T1, low(RAMEND) out SPL, T1 ; RSTR, ISTR, RSER, RCLK are port B outputs ldi T1, (1<